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cy62156esl mobl ? 8-mbit (512 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-54995 rev. *d revised may 13, 2013 8-mbit (512 k 16) static ram features high speed: 45 ns wide voltage range: 2.2 v to 3.6 v and 4.5 v to 5.5 v ultra low standby power ? typical standby current: 2 ? a ? maximum standby current: 8 ? a ultra low active power ? typical active current: 1.8 ma at f = 1 mhz easy memory expansion with ce 1 , ce 2 , and oe features automatic power down when deselected cmos for optimum speed and power available in pb-free 48-ball very fine-pitch ball grid array (vfbga) packages functional description the cy62156esl is a high performance cmos static ram organized as 512k words by 16 bits. this device features advanced circuit design to provid e ultra low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. place the device in standby mode when deselected (ce 1 high or ce 2 low). the input or output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when the device is deselected (ce 1 high or ce 2 low), the outputs are disabled (oe high), byte high enable and byte low enable are disabled (bhe , ble high), or a write operation is active (ce 1 low, ce 2 high and we low). to write to the device, take chip enable (ce 1 low and ce 2 high) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ) is written into the location spec ified on the address pins (a 0 through a 18 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 18 ). to read from the device, take chip enable (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the truth table on page 11 for a complete description of read and write modes. logic block diagram 512 k 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 ce we bhe a 16 a 0 a 1 a 9 a 10 ble a 17 a 18
cy62156esl mobl ? document number: 001-54995 rev. *d page 2 of 16 contents pin configurations ........................................................... 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 6 data retention waveform ................................................ 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagrams .......................................................... 13 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 16 worldwide sales and design s upport ......... .............. 16 products .................................................................... 16 psoc solutions ......................................................... 16
cy62156esl mobl ? document number: 001-54995 rev. *d page 3 of 16 pin configurations figure 1. 48-ball vfbga pinout (top view) [1] product portfolio product range v cc range (v) [2] speed (ns) power dissipation operating i cc , (ma) standby, i sb2 ( ? a) f = 1mhz f = f max typ [3] max typ [3] max typ [3] max cy62156esl industrial 2.2 v to 3.6 v and 4.5 v to 5.5 v 45 1.8 3 18 25 2 8 we v cc a 11 a 10 nc a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe v ss a 7 i/o 0 bhe ce 2 a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc a 18 nc 3 26 5 4 1 d e b a c f g h a 16 a 17 notes 1. nc pins are not connected on the die. 2. datasheet specifications are not guaranteed for v cc in the range of 3.6 v to 4.5 v. 3. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c.
cy62156esl mobl ? document number: 001-54995 rev. *d page 4 of 16 maximum ratings exceeding the maximum ratings may impair the useful life of the device. user guidelines are not tested. storage temperature ............. .............. .... ?65 c to + 150c ambient temperature with power applied ........................................ ?55 c to + 125 c supply voltage to ground potentia l ............. ..?0.5 v to 6.0 v dc voltage applied to outputs in high z state [4, 5] ........................................?0.5 v to 6.0 v dc input voltage [4, 5] ....................................?0.5 v to 6.0 v output current into outputs (low) ............................ 20 ma static discharge voltage (mil-std-883, method 3015) ................................. > 2,001v latch up current ................................................... > 200 ma operating range device range ambient temperature v cc [6] cy62156esl industrial ?40 c to +85 c 2.2 v to 3.6 v, and 4.5 v to 5.5 v electrical characteristics over the operating range parameter description test conditions 45 ns unit min typ [1] max v oh output high voltage 2.2 < v cc < 2.7 i oh = ?0.1 ma 2.0 ? ? v 2.7 < v cc < 3.6 i oh = ?1.0 ma 2.4 ? ? 4.5 < v cc < 5.5 i oh = ?1.0 ma 2.4 ? ? v ol output low voltage 2.2 < v cc < 2.7 i ol = 0.1 ma ? ? 0.4 v 2.7 < v cc < 3.6 i ol = 2.1ma ? ? 0.4 4.5 < v cc < 5.5 i ol = 2.1ma ? ? 0.4 v ih input high voltage 2.2 < v cc < 2.7 1.8 ? v cc + 0.3 v 2.7 < v cc < 3.6 2.2 ? v cc + 0.3 4.5 < v cc < 5.5 2.2 ? v cc + 0.5 v il input low voltage 2.2 < v cc < 2.7 ?0.3 ? 0.6 v 2.7 < v cc < 3.6 ?0.3 ? 0.8 4.5 < v cc < 5.5 ?0.5 ? 0.8 i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax , i out = 0 ma, cmos levels ?1825ma f = 1 mhz ? 1.8 3 i sb1 automatic ce power down current ? cmos inputs ce 1 > v cc ?? 0.2 v, ce 2 < 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = f max (address and data only), f = 0 (oe , bhe , ble and we ), v cc = v cc(max) ?28 ? a i sb2 [7] automatic ce power down current ? cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v , v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc(max) ?28 ? a notes 4. v il (min) = ?2.0 v for pulse durations less than 20 ns. 5. v ih (max) = v cc + 0.75 v for pulse durations less than 20 ns. 6. full device ac operation assumes a 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 7. only chip enables (ce 1 and ce 2 ) need to be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating.
cy62156esl mobl ? document number: 001-54995 rev. *d page 5 of 16 capacitance parameter [8] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [8] description test conditions 48-ball bga unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 72 ? c/w ? jc thermal resistance (junction to case) 8.86 ? c/w ac test loads and waveforms figure 2. ac test loads and waveforms v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: th venin equivalent all input pulses r th r1 th parameters 2.5 v 3.0 v 5.0 v unit r1 16667 1103 1800 ? r2 15385 1554 990 ? r th 8000 645 639 ? v th 1.20 1.75 1.77 v note 8. tested initially and after any design or process changes that may affect these parameters.
cy62156esl mobl ? document number: 001-54995 rev. *d page 6 of 16 data retention characteristics over the operating range parameter description conditions min typ [9] max unit v dr v cc for data retention 1.5 ? ? v i ccdr [10] data retention current ce 1 > v cc ? 0.2 v, ce 2 < 0.2 v , v in > v cc ? 0.2 v or v in < 0.2 v, v cc = 1.5 v ?25 ? a t cdr [11] chip deselect to data retention time 0??ns t r [12] operation recovery time 45 ? ? ns data retention waveform figure 3. data retention waveform v cc(min) t cdr v dr > 1.5 v data retention mode t r v cc(min) ce 1 v cc ce 2 or notes 9. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 10. only chip enables (ce 1 and ce 2 ) need to be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating. 11. tested initially and after any design or proce ss changes that may affect these parameters. 12. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) > 100 ? s.
cy62156esl mobl ? document number: 001-54995 rev. *d page 7 of 16 switching characteristics over the operating range parameter [13] description 45 ns unit min max read cycle t rc read cycle time 45 ? ns t aa address to data valid ? 45 ns t oha data hold from address change 10 ? ns t ace ce 1 low and ce 2 high to data valid ? 45 ns t doe oe low to data valid ? 22 ns t lzoe oe low to low z [14] 5 ? ns t hzoe oe high to high z [14, 15] ? 18 ns t lzce ce 1 low and ce 2 high to low z [14] 10 ? ns t hzce ce 1 high and ce 2 low to high z [14, 15] ? 18 ns t pu ce 1 low and ce 2 high to power up 0 ? ns t pd ce 1 high and ce 2 low to power down ? 45 ns t dbe ble /bhe low to data valid ? 22 ns t lzbe ble /bhe low to low z [14] 5 ? ns t hzbe ble /bhe high to high z [14, 15] ? 18 ns write cycle [16] t wc write cycle time 45 ? ns t sce ce 1 low and ce 2 high to write end 35 ? ns t aw address setup to write end 35 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 35 ? ns t bw ble /bhe low to write end 35 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [14, 15] ? 18 ns t lzwe we high to low z [14] 10 ? ns notes 13. test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing ref erence levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the figure 2 on page 5 . 14. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 15. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high-impedance state. 16. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe , ble or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive . the data input setup and hold timing must be referenced to th e edge of the signal that terminates the write.
cy62156esl mobl ? document number: 001-54995 rev. *d page 8 of 16 switching waveforms figure 4. read cycle no. 1: address transition controlled [17, 18] figure 5. read cycle no. 2: oe controlled [18, 19] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzbe t lzbe t hzce t dbe oe ce 1 address ce 2 bhe /ble data out v cc supply current high i cc i sb impedance notes 17. the device is continuously selected. oe , ce 1 = v il , bhe , ble , or both = v il , and ce 2 = v ih . 18. we is high for read cycle. 19. address valid before or similar to ce 1 , bhe , ble transition low and ce 2 transition high.
cy62156esl mobl ? document number: 001-54995 rev. *d page 9 of 16 figure 6. write cycle no 1: we controlled [20, 21, 22] figure 7. write cycle 2: ce controlled [20, 21, 22] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data t bw note 23 ce 1 address ce 2 we data i/o oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data t bw t sa note 23 ce 1 address ce 2 we data i/o oe bhe /ble notes 20. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe , ble or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a writ e by going inactive. the data input setup and hold timing must be referenced to th e edge of the signal that terminates the write. 21. data i/o is high impedance if oe = v ih . 22. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 23. during this period, the i/os are in output state. do not apply input signals.
cy62156esl mobl ? document number: 001-54995 rev. *d page 10 of 16 figure 8. write cycle 3: we controlled, oe low [24] figure 9. write cycle 4: bhe /ble controlled, oe low [24] switching waveforms (continued) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 25 ce 1 address ce 2 we data i/o bhe /ble t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe note 25 ce 1 address ce 2 we data i/o bhe /ble notes 24. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 25. during this period, the i/os are in output state. do not apply input signals.
cy62156esl mobl ? document number: 001-54995 rev. *d page 11 of 16 truth table ce 1 ce 2 we oe bhe ble inputs/outputs mode power h x x x x x high z deselect/power down standby (i sb ) x l x x x x high z deselect/power down standby (i sb ) l h x x h h high z output disabled active (i cc ) l h h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h h l h l data out (i/o 0 ?i/o 7 ); high z (i/o 8 ?i/o 15 ) read active (i cc ) lhhllhhigh z (i/o 0 ?i/o 7 ); data out (i/o 8 ?i/o 15 ) read active (i cc ) l h h h l h high z output disabled active (i cc ) l h h h h l high z output disabled active (i cc ) l h h h l l high z output disabled active (i cc ) l h l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l h l x h l data in (i/o 0 ?i/o 7 ); high z (i/o 8 ?i/o 15 ) write active (i cc ) lhlxlhhigh z (i/o 0 ?i/o 7 ); data in (i/o 8 ?i/o 15 ) write active (i cc )
cy62156esl mobl ? document number: 001-54995 rev. *d page 12 of 16 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 45 CY62156ESL-45BVXI 51-85150 48- ball vfbga (pb-free) industrial temperature range: i = industrial pb-free package type: bv = 48-ball vfbga speed grade: 45 ns low power process technology: e = 90 nm buswidth: 6 = 16 density: 5 = 8-mbit family code: mobl sram family company id: cy = cypress cy 45 bv 621 5 6 e sl x i -
cy62156esl mobl ? document number: 001-54995 rev. *d page 13 of 16 package diagrams figure 10. 48-ball vfbga (6 8 1 mm) bv48/bz48 package outline, 51-85150 51-85150 *h
cy62156esl mobl ? document number: 001-54995 rev. *d page 14 of 16 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable ram random access memory sram static random access memory vfbga very fine-pitch ball grid array we write enable symbol unit of measure c degree celsius mhz megahertz a microampere s microsecond ma milliampere mm millimeter ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy62156esl mobl ? document number: 001-54995 rev. *d page 15 of 16 document history page document title: cy62156esl mobl ? , 8-mbit (512 k 16) static ram document number: 001-54995 rev. ecn no. orig. of change submission date description of change ** 2751673 vkn 08/13/09 new data sheet *a 2899866 aju 03/26/10 removed inactive parts from ordering information. updated package diagram *b 3109032 aju 12/13/2010 obsolete document. *c 3903222 aju 02/19/2013 changed from obsolete to active. removed all references of tsop packages across the document and added 48-ball vfbga package related information in the corresponding places. updated features . updated functional description . updated logic block diagram . updated ordering information (updated part numbers) and added ordering code definitions . updated package diagrams : removed spec 51-85087 and spec 51-85183. added spec 51-85150. added acronyms and units of measure . updated in new template. *d 3996550 memj 05/13/2013 changed stat us from preliminary to final.
document number: 001-54995 rev. *d revised may 13, 2013 page 16 of 16 mobl is a registered trademark and more battery life is a trademark of cypress semiconductor. all products and company names me ntioned in this document may be the trademarks of their respective holders. cy62156esl mobl ? ? cypress semiconductor corporation, 2009-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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